Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input.
The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?
Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits).
If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifters. I don't know how the circuit area compares between the two approaches--two more complex stages vs six simpler stages--but I suspect the two-stage approach wins.
Northstar made an S-100 card which did FP math, using BCD arithmetic. It had a ucode ROM and a 4b (single digit) ALU, and a few small RAMs to hold the digits. If I remember correctly you could program it to select how many digits you wanted in your representation, up to 14 digits. It did everything one digit at a time, and it had a 256 byte ROM to carry out any digit*digit product in one cycle. For normalization no data was moved -- just the pointer to the appropriate digit was incremented or decremented.
That's a very interesting board! It came out in 1976 (four years before the 8087) and cost $499 assembled, equivalent to $2900 in current dollars, so it was expensive. It was really a decimal processor built from simple TTL parts, and had four microcoded instructions: add, subtract, multiply, and divide. Arithmetic used the 74LS181, the very popular ALU chip. (It did multiplication with repeated addition; there's no ROM with digit products, unless that was a later version.) The "small RAM" was very small by modern standards: four 4-bit registers that each held 16 digits. Each register was implemented with a 74S189 chip.
The microcode is available, so it would be a fun project to write a simulator that runs the microcode.
My mistake -- what I wrote was from memory so I got the bit wrong about the multiplier ROM. I must have confused that detail with the design of the Wang 2200 computer, which had double precision BCD float math and did in fact have a 4b x 4b multiplier ROM.
Yes - I was just trying to give things a "this is interesting, so upvote & discuss!" kick. In the absence of Ken popping up with good "Author here for your 8087 questions" comment.
Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input.
The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?
Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits).
If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifters. I don't know how the circuit area compares between the two approaches--two more complex stages vs six simpler stages--but I suspect the two-stage approach wins.
Northstar made an S-100 card which did FP math, using BCD arithmetic. It had a ucode ROM and a 4b (single digit) ALU, and a few small RAMs to hold the digits. If I remember correctly you could program it to select how many digits you wanted in your representation, up to 14 digits. It did everything one digit at a time, and it had a 256 byte ROM to carry out any digit*digit product in one cycle. For normalization no data was moved -- just the pointer to the appropriate digit was incremented or decremented.
https://s100computers.com/Hardware%20Folder/NorthStar/FP%20B...
That's a very interesting board! It came out in 1976 (four years before the 8087) and cost $499 assembled, equivalent to $2900 in current dollars, so it was expensive. It was really a decimal processor built from simple TTL parts, and had four microcoded instructions: add, subtract, multiply, and divide. Arithmetic used the 74LS181, the very popular ALU chip. (It did multiplication with repeated addition; there's no ROM with digit products, unless that was a later version.) The "small RAM" was very small by modern standards: four 4-bit registers that each held 16 digits. Each register was implemented with a 74S189 chip.
The microcode is available, so it would be a fun project to write a simulator that runs the microcode.
Manual and schematics are here if anyone is looking for them: https://bitsavers.org/pdf/northstar/boards/North_Star_Floati...
My mistake -- what I wrote was from memory so I got the bit wrong about the multiplier ROM. I must have confused that detail with the design of the Wang 2200 computer, which had double precision BCD float math and did in fact have a 4b x 4b multiplier ROM.
https://www.wang2200.org/
(I'm the guy behind the wang2200.org domain)
Must…resist…clicking link… I’ve got a lot to today and this is like carefully crafted bait to tie me up for the next 4 hours. :-)
Closely related, 8 days ago, 138 points & 28 comments:
https://news.ycombinator.com/item?id=48519011 (about the 8087's adder)
That's a different article by the same author, Ken Shirriff
https://www.righto.com/2020/05/die-analysis-of-8087-math-cop...
https://www.righto.com/2026/06/intel-8087-adder-reverse-engi...
Yes - I was just trying to give things a "this is interesting, so upvote & discuss!" kick. In the absence of Ken popping up with good "Author here for your 8087 questions" comment.
I guess he didn't pop up because the article is 6 years old.
https://news.ycombinator.com/item?id=23362673
I'm here now if anyone has questions. I can't be online all the time :-)
Re-post that comment top-level, so folks can see that the Big Name is now on stage. ;)
It's German for