GPT-Synopsys brings together OpenAI frontier models with Synopsys' EDA technology and domain expertise, enabling the specialized model [to] directly operate Synopsys' tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
“Agents will do all the engineering work. Engineers will delegate and review.” Lol, no, what the engineers are gonna do is get laid off.
The problem with "engineers will review" is: Critical review requires expertise. Expertise requires experience. Experience comes from building. Builders build because they like to build. So when builders are asked to do nothing but review, they will eventually tire of their jobs and leave, sometimes not just the job, but the industry entirely. The lower the quality of the agents' output, the faster this will happen.
Why does this sound very much like the argument toward full self-driving? If drivers need to be watchful of mostly autonomous ones, they get bored and lose attention or sometimes take nap in front of the steering wheel. Waymo came out of an extension of this argument..
> So when builders are asked to do nothing but review, they will eventually tire of their jobs and leave, sometimes not just the job, but the industry entirely.
I do agree that a lot of engineers who want to do everything the old manual way are about to get really frustrated.
I don't think this is as universal as you say. There are a lot of engineers who are excited and happy to use these tools. Leave the bubbles of Hacker News, Lobsters, and similar sites and a lot of people are embracing these tools.
You also skipped the step where someone needs to direct the design. In the pre-LLM era it was commonly accepted that engineers who advanced to very senior roles would become less connected to the implementation details and more connected to steering, reviewing, and directing. Only a few years ago Hacker News was full of anecdotes about staff engineers who barely wrote code any more. Those people will have no problem switching to a new world where LLMs are handling implementation details.
The point stands, though. Senior engineers can detach themselves from implementation details because more junior engineers still do the hard parts. In the AI case, agents are the "engineers". Eventually all competency will be within AI domain and none within human one.
Why people are so eager to surrender their birthright to the machines for the mess of pottage?
In cartoons you'd have this concept where someone is sawing away with great energy on a branch while sitting on the dead side of the saw. This is that concept, but on a much larger scale.
If people want to build stuff they can, they just may not be paid for it. But if we don't need to pay anyone to do anything then it also doesn't matter that you aren't being paid, as you'd have all you need, and you can spend your time tinkering away on low tech/cottagecore enterprises like designing an ASIC or making bread.
You can do this for any company now. Any company not announcing this to boost their stock is foolish, ride the train with the crowd.
GPT-Company name brings together frontier AI models with Company's XYZ technology and domain expertise, enabling the specialized model [to] directly operate Company's tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
Eventually... But it is materially relevant if that happens in 2 years or 10.
While I think SWEs(yeah, not HW/chip but that's not my field) are cooked in 5 years, I think we'll be quite busy in the meantime fixing all the bugs that AI finds.
> we'll be quite busy in the meantime fixing all the bugs that AI finds.
Maybe that's the job of software engineering moving forward.
Client: Hey, we have got these 125 microservices created by our agents and for the last 25 days they got stuck and can't add any new feature without breaking things, can you take this?
Eng: Sure, lets sign a 24 month contract, my rate is 250$/hr
Today's frontier models can't even handle 100% of the SWE benchmarks that have been around for longer than they've been training the models. Companies that are benchmaxxing their models against the benchmarks haven't even been able to get them to 100%.
I've been using Astra and Opus 5.5 all week and I still have to intervene and tell them to do something different all the time.
I think the people whose SWE jobs consisted of simple features, bug fixes, or tweaking .toml until the server works are on their way out.
Someone needs to steer the LLMs around for now, though. There is a very long tail of non-trivial work and expertise that can't yet be replaced by a CEO telling the LLM to make the product work. There are many CEOs trying to do that right now and, outside of very simple CRUD apps, it doesn't work yet.
> Today's frontier models can't even handle 100% of the SWE benchmarks that have been around for longer than they've been training the models. Companies that are benchmaxxing their models against the benchmarks haven't even been able to get them to 100%.
Given how flawed the benchmarks are (see for example https://epoch.ai/benchmarks/deepswe/review), not even the mythical 10x developer is gonna get 100% on these benchmarks.
That isn't actually relevant. They create problems, but when confronted with them and asked to fix them, my experience is that they can fix them very effectively. I haven't had an AI session get "stuck" on me, not being able to solve a problem in over a year.
The challenge as I see it is in shifting checks further left, but actual mitigation is just not really an issue any more.
Chips design is expensive. Partly because of engineering costs, partly because of manufacturing costs.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
For each Design Engineer, there are 3 Design Validation Engineers because going to fabrication is very expensive and it is unlike software where you can just do a git push and wait for the CI/CD pipeline to deploy code within minutes at no additional costs.
When TSMC capacity is already sold out for a couple of years, and demand just for plain RAM is through the roof, where will these "more chips" be actually fabbed?
> more chips will be designed, so maybe this will partially offset job loses.
This is HN mentality. But it is not how it always works. The first thought isn't we can make more money tomorrow by building more faster. It is we can make more money today by laying off all the people that we don't need now. Short-termism is the rule.
I think that’s more the norm in stability, where the economy when not a lot is happening/changing/improving, and so the economy is focused on efficiency as a method of competition. We are squarely not in efficiency mode right now, we’re in explore as fast as possible mode, as a lot of old underlying assumptions have changed, and there’s a huge amount of work to be done in reworking everything for the new assumptions. That means lots of opportunities, lots of money flying around, and bean counters getting outcompeted by people who’re focused on doing new things. Being too conservative does not serve you well in this regime. My two cents, anyway, I don’t think overall massive job losses are on the menu anytime soon, but massive job displacement/swapping, very likely.
My observation is even if AI takes 80-90% of my job, the remaining 10% is still going to be more relevant to keeping the company going than other people's 100%.
I wish this was hubris, but no. I would genuninely be happy to not have to do other people's work for them on top of mine.
I wish I was arrogant. Or alternatively I wish I was surrounded by arrogant coworkers who at least took some pride in the quality and quantity of their work.
Not saying everyone is like this, but plenty enough are.
But hey, at least folks unburdened by the pressure to ship anything have plenty of time to play office politics.
Aren't hardware design issues incredibly costly? I highly doubt they're going to "dark software factory" it or they'll be eaten alive by failed launches, product recalls, lawsuits.
I worry that even the electronics industry is falling into the fear of being agentic or being left in the dust. AI slop is already weird for programs.. I wouldn't want that in hardware.
I see this as worse for junior engineers than senior. Right now junior engineers don't have the experience to spot issues, ans if gpt-synopsys gives an answer they don't know to question it. It Will also be better than many junior engineers out of the box..
So junior engineers dont get a chance to learn and progress to senior. Senior engineers (for now) will interact with these agents and review the output, ans can direct them. Again, until it becomes better at that.
Interesting times. A lot has happened in a year..where will we be a year from now?
We just buried an ASIC design that was nearly finished.
Reason: There was a deviation that would've needed a mask change, but because of AI chip demand, the manufacturer wanted so much money for it, that we said screw it.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
> Manufacturers choosing not to scale with demand or not being able to scale with demand
In a vacuum, that would make sense.
But looking at how the industry works, the number of defunct companies, and how the whole industry got concentrated on the conservative companies, you start to understand that the reason they still exist is mainly because they don't ride fad waves.
It's not like chip manufacturing is a spot instance on AWS that you spin up and down when needed; these are multi-year, multi-billion dollar investments that require long-term demand studies. The AI approach of requesting a whole fab of demand for the next 5 years with a letter from Jason Hwang that says "trust it, bro" does not bring as much confidence as it appears.
There’s a lot of other boring chips on a server motherboard beyond the RAM and CPU that share older processes with everyone else making silicon. Stuff like power management ICs needed to bring up power to a chip in the right order, which were an annoyance even before COVID and AI.
The whole supply chain is so focused on RAM/GPUs that it's affecting everything. I've seen random sensors 3x in price because the company making them has shifted their manufacturing focus.
3D printers are a nice analogy, but the complexity level is orders of magnitude higher for chip making, besides the stability of the environment requirements.
From an investment perspective, I think chip fabs TSMC, Intel, and Samsung will benefit from better AI chip design tools.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
Maybe some day, a kid in his garage can just tell an AI to design a custom chip, send it to TSMC, and get the chip in the mail in a few weeks.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
This might make some sense if, the cost of any change in design vs requirement wouldn't cost $30-50M in mask and tape-out alone. That doesn't count the first wafer 'hot lots' just to get the design's first wafer out in only 3 months, or the bringup and modified test equipment to validate the design, or the corners testing and optimization, or the package tooling, or... Those can easily be additional $10Ms and that's per design, if you do a full mask change. If you can "fix it in metal", you might get that down to just $10M and 1 month?
This isn't software. The time, labor, and equipment costs of the first wafer dwarf the redesign cost, so it makes sense to get it right the first time. What if every build, compile, and link cost you $10M and 1 month? How would that change your work flow?
Most of the "AI" design tools today are focused on verification, validation and layout, which makes a lot of sense. They might help with architecture in the future (or making something high yield AND easy to fix in metal)?
You could run a small design on an MPW shuttle to reduce these costs, but your TTM get's longer, the yields won't be as high, and if you go to mass production you still face the huge mask costs.
Another place this might make some sense is reworking old large die 130nm designs on 8" wafers to be newer 28mm designs on 12", there are a LOT of those. The mask costs are lower, the design is well understood with lots of process margin, and wafer/yield costs could be modeled and favorable. Of course analog scaling is a whole separate kettle of fish.
But then you are assuming the current way is optimal. Why can’t we have a 3d-printer-style contraption for chips?
If people have millions of new chip designs that need making, perhaps that will be motivation to invent a new way of making chips. It might not be better at manufacturing a billion of the same chip, but maybe it’s better at producing a billion different chips. Then every HFT could have their own chip and people could try out all kinds of new designs without committing a fortune.
Can 3D printers print with 1 micrometer (not millimeter) accuracy? 1 micron gets you things like the original 8086. Oh wait, current best desktop printers get like 100 micron (0.1 mm) accuracy. So scale up what we have now 100x in terms of accuracy (imagine how much bigger / more precise the motors, magnets, everything has to be). EASILY 10-50x the cost of a good home 3D printer today - say $50K. And 8086? Your phone is faster than probably 50-100 of them in parallel today) - so $100K (materials aren't cheap) to print a series of chips that were insanely obsolete 20 years ago and 1 $500 fpga could run circles around. Then scale that up at least another 50x to get semi-competitive (20 nm). There's a reason they put fabs in places like Arizona where there are relatively few earthquakes... Even the garbage truck driving past your house could damage your chip.
As far as home printing stuff: the clean room requirements are INSANE: just the HF (hydrofluoric acid) is crazy bad stuff that you could NOT get certified for general consumer use, no way, no how. And even if you did, you'd be crazy to buy something that comes with HF as part of the process.. And that's just ONE bad, bad chemical used by TSMC all the time.
FPGAs are the "faster-than-software / can make a custom chip" compromise - companies like Intel used to (not sure if they still do) use a ton of FGPAs to simulate new chip designs. Precisely because manufacturing state-of-the-art chips is so hard.
Think how long it takes for a 3D printer to finish a single design with 0.1mm resolution. Now scale that down to 10nm. The time to complete goes up by 10^12. A 1 minute design would scale to 2M years.
There's a reason e-beam lithography is only used to make masks, and why it's one of the most expensive parts of the manufacture.
E-beam lithography absolutely is/can be used to manufacture one-off chips.
The problem isn't lithography, though, it's all of the adjacent processes (ion implantation and a dozen other things) that are fab/process-specific and require even more complicated/expensive equipment.
Shuttle runs give you a true-to-process tapeout and are dirt cheap, so only universities and the like bother with direct-write.
> These chips still need to be physically made at TSMC, Intel, or Samsung.
That's for the most advance tech (sub 10nm and such). There is a lot of fab for chips that do not require the latest and greatest. If LLMs make it easier / more accessible to design ASIC, I think those fabs will be the one who will benefit the most.
Only tangentially related but many many years ago, I spent a good chunk of a summer internship at synopsys fixing gcc warnings in one of their products. The codebase was huge, with many parts of it more than a decade old at that point. I learned a lot about obscure corners of C. These days a frontier model could do that job in a few days (or maybe just one day if the build and testing process has been sped up - it took several hours on a dedicated cluster back then).
> I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
... > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
EXACTLY, prepare to self deport immediately, push <proceed> to execute
Also the other way around (Cadence shipping Synopsys IP). Big chips wind up with IP blocks from many sources and (at least usually) the right people get paid. And EDA engineers bounce around between Cadence, Synopsys, and Mentor (now Siemens EDA).
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
A question to those active in chip design industry: Are formal methods and formally proving a design more prevalent and normal in this industry compared to general software development?
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
There are tools for formal verification of design input, and they are being used, but not for everything.
Why there are still errata for silicon
1. Writing a formal specification of your intended behavior is hard and the best verification tool doesn't help when your assertions don't encode the required or intended behavior. So even with 100% formal coverage, you would still get erratas. And some people don't write any formal verification, instead working with a simulation based approach (either hand-written test cases or random stimulus simulation)
2. Computation complexity of formal verification is exponential. At some point you simply can't formally prove the behavior of a design, because it just won't run on your server.
3. There's different levels of formal verification, not all of them are in the spec -> behavior path. For example, you could classify automated checks like logic equivalence between the synthesis netlist and RTL code as a formal verification. But that checks if the optimizer in the synthesis tool was correct, not that you wrote the correct RTL.
It’s called design verification, formal proofs happen mostly at the EDA tool level and largely already automated. Design verification focus on functional correctness of the chip for its intended use case
Compared to software formal methods have greater adoption. But there are a lot of things that fall under the “formal” umbrella.
The most common type that is used would probably be logical equivalence checking. Proving RTL and a netlist are equivalent is useful for catching synthesis bugs.
Or proving two netlists are equivalent after inserting test functions directly into a netlist, or some other netlist edit.
Property checking is what I use the most. You can check these during simulation which I wouldn’t call “formal” but you can also prove them using tools that use SAT solvers and whatnot to prove things mathematically.
As always, the tricky part of verification is writing the correct test or model. With formal we can use SystemVerilog assertions to write properties and sequences, but the difficulty in getting them right goes from trivial -> inscrutable very quickly.
It’s extreme easy to write assertions that pass and never realize your assertion was not doing what you thought and you weren’t proving what you meant to.
I haven’t used some of the more advanced tools so maybe they have ways to make this easier. But because of this I tend to just write assertions that are pretty easy to understand at a glance, and therefore closer to the trivial side of things.
If a peer has to solve a sudoku puzzle in their head to understand your work, then it’s unlikely the peer review will be worth anything. So I do what I can to make my work understandable at a glance (from a competent peer in the industry).
Of course making something simple can be quite challenging and often takes more time than leaving something complex and opaque.
I’ve never been involved in the foundry side of the work, and for ASICs, that is often half of the schedule.
Having written a lot of Tcl glue for PrimeTime and ICC, the hard part was never writing the constraints, it was knowing which timing violation to actually believe.
Apparently SNPS share price gone up a little bit because of this. However, the rise didn't compensate their loss over the years. I keep wondering why EDA companies didn't get the hype like AI labs and Chip design companies.
To maximize hype, a company has to be losing money, but with a story about how it will eventually be making massive money. Stable companies that make some money, are growing steadily but with no hope of growing massively, aren't so exciting, and that's what EDA companies are.
I remember the stock taking a beating after Kimi K3 created all that buzz about the open model designing chips that could run itself (even though the chip in question seemed small in today's standard of massive AI chips). It was only a matter of time before Synopsys released an offering like this. I can almost see the meeting where the C suite demanded working with an external partner over anything in-house they could build.
Why the overall market cap is smaller than both Synopsys and Ansys combined before the merger still beats me tho.
I don't know how much of a difference this makes in practice. Creating the photomasks and proving the resulting silicon is still the predominant bottleneck in chip design.
If you have a flaw in the RTL and need to do a respin it can add 3+ months to the lead time of a new product. Allowing GPT to iterate through this kind of cycle seems economically infeasible unless you have an enormous amount of spare EUV capacity (you don't).
Would be really nice honestly. But I don't think it will be coming anytime soon, it's just too expensive to build a chip.
The one-time costs for masks are just much more expensive as for PCBs, so wafer shuttle services are still really expensive when pooled PCBs are really cheap.
And any machines that would be cheaper for prototyping (direct laser writing or direct e-beam writing) don't scale to mass production.
You can already make (tiny) chips for a somewhat affordable cost with tiny tapeout.
But that's still not nearly as cheap as PCB prototypes and with much longer wait times.
You get your non-deterministic process (hired humans or LLMs) to create deterministic scripts (='generators' in EDA terms), which can then be audited, corrected, etc.
DRC/LVS/PEX/SPICE are deterministic, but the tools themselves are not without faults.
Physical design (what this seems to be targeting) already uses non-deterministic algorithms because floorplanning, placement, and routing are all difficult problems to solve with a deterministic algorithm. Introducing probabalistic approaches helps to find the right fit within the constraints.
The problem with "engineers will review" is: Critical review requires expertise. Expertise requires experience. Experience comes from building. Builders build because they like to build. So when builders are asked to do nothing but review, they will eventually tire of their jobs and leave, sometimes not just the job, but the industry entirely. The lower the quality of the agents' output, the faster this will happen.
Why does this sound very much like the argument toward full self-driving? If drivers need to be watchful of mostly autonomous ones, they get bored and lose attention or sometimes take nap in front of the steering wheel. Waymo came out of an extension of this argument..
> So when builders are asked to do nothing but review, they will eventually tire of their jobs and leave, sometimes not just the job, but the industry entirely.
I do agree that a lot of engineers who want to do everything the old manual way are about to get really frustrated.
I don't think this is as universal as you say. There are a lot of engineers who are excited and happy to use these tools. Leave the bubbles of Hacker News, Lobsters, and similar sites and a lot of people are embracing these tools.
You also skipped the step where someone needs to direct the design. In the pre-LLM era it was commonly accepted that engineers who advanced to very senior roles would become less connected to the implementation details and more connected to steering, reviewing, and directing. Only a few years ago Hacker News was full of anecdotes about staff engineers who barely wrote code any more. Those people will have no problem switching to a new world where LLMs are handling implementation details.
The point stands, though. Senior engineers can detach themselves from implementation details because more junior engineers still do the hard parts. In the AI case, agents are the "engineers". Eventually all competency will be within AI domain and none within human one.
Why people are so eager to surrender their birthright to the machines for the mess of pottage?
In cartoons you'd have this concept where someone is sawing away with great energy on a branch while sitting on the dead side of the saw. This is that concept, but on a much larger scale.
If people want to build stuff they can, they just may not be paid for it. But if we don't need to pay anyone to do anything then it also doesn't matter that you aren't being paid, as you'd have all you need, and you can spend your time tinkering away on low tech/cottagecore enterprises like designing an ASIC or making bread.
I am very skeptical about benevolence of our future overlords, humans or AI, towards people they don't need anymore.
You can do this for any company now. Any company not announcing this to boost their stock is foolish, ride the train with the crowd.
GPT-Company name brings together frontier AI models with Company's XYZ technology and domain expertise, enabling the specialized model [to] directly operate Company's tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
We're not Hershey's the Chocolate company based in Hershey PA...
We're WWW.hersheys.COM the fully Web integrated Global Information cocoa delivery company.
Chocolate lovers will delegate chocolate eating objectives, GPT-Hersheys will automatically eat the chocolate.
Don't hate the player hate the game
Eventually... But it is materially relevant if that happens in 2 years or 10.
While I think SWEs(yeah, not HW/chip but that's not my field) are cooked in 5 years, I think we'll be quite busy in the meantime fixing all the bugs that AI finds.
> we'll be quite busy in the meantime fixing all the bugs that AI finds.
Maybe that's the job of software engineering moving forward.
Client: Hey, we have got these 125 microservices created by our agents and for the last 25 days they got stuck and can't add any new feature without breaking things, can you take this?
Eng: Sure, lets sign a 24 month contract, my rate is 250$/hr
Client: Sounds good
Eng: So I prompted Claude to turn the 125 microservices into a single Erlang program. Better not tell the client.
Do you think that even today's frontier models are unable to handle this task?
Today's frontier models can't even handle 100% of the SWE benchmarks that have been around for longer than they've been training the models. Companies that are benchmaxxing their models against the benchmarks haven't even been able to get them to 100%.
I've been using Astra and Opus 5.5 all week and I still have to intervene and tell them to do something different all the time.
I think the people whose SWE jobs consisted of simple features, bug fixes, or tweaking .toml until the server works are on their way out.
Someone needs to steer the LLMs around for now, though. There is a very long tail of non-trivial work and expertise that can't yet be replaced by a CEO telling the LLM to make the product work. There are many CEOs trying to do that right now and, outside of very simple CRUD apps, it doesn't work yet.
> Today's frontier models can't even handle 100% of the SWE benchmarks that have been around for longer than they've been training the models. Companies that are benchmaxxing their models against the benchmarks haven't even been able to get them to 100%.
Is average developer 100% the benchmarks ?
Given how flawed the benchmarks are (see for example https://epoch.ai/benchmarks/deepswe/review), not even the mythical 10x developer is gonna get 100% on these benchmarks.
Well, I let him do some stuff in kube. The architecture is a complete mess.
Today’s frontier models create the problem.
That isn't actually relevant. They create problems, but when confronted with them and asked to fix them, my experience is that they can fix them very effectively. I haven't had an AI session get "stuck" on me, not being able to solve a problem in over a year.
The challenge as I see it is in shifting checks further left, but actual mitigation is just not really an issue any more.
Actually, I do this too, but I find the first round and the fix round are still way more complex than an original right round. If that makes sense.
What problem? They keep finding security bugs that humans couldn't for decades.
So ask them to fix the problems in a targeted way.
Chips design is expensive. Partly because of engineering costs, partly because of manufacturing costs.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
For each Design Engineer, there are 3 Design Validation Engineers because going to fabrication is very expensive and it is unlike software where you can just do a git push and wait for the CI/CD pipeline to deploy code within minutes at no additional costs.
So let's see.
The wish granting machine won't need the engineers for that. You'll just end up paying for the devices.
When TSMC capacity is already sold out for a couple of years, and demand just for plain RAM is through the roof, where will these "more chips" be actually fabbed?
> more chips will be designed, so maybe this will partially offset job loses.
This is HN mentality. But it is not how it always works. The first thought isn't we can make more money tomorrow by building more faster. It is we can make more money today by laying off all the people that we don't need now. Short-termism is the rule.
I think that’s more the norm in stability, where the economy when not a lot is happening/changing/improving, and so the economy is focused on efficiency as a method of competition. We are squarely not in efficiency mode right now, we’re in explore as fast as possible mode, as a lot of old underlying assumptions have changed, and there’s a huge amount of work to be done in reworking everything for the new assumptions. That means lots of opportunities, lots of money flying around, and bean counters getting outcompeted by people who’re focused on doing new things. Being too conservative does not serve you well in this regime. My two cents, anyway, I don’t think overall massive job losses are on the menu anytime soon, but massive job displacement/swapping, very likely.
My observation is even if AI takes 80-90% of my job, the remaining 10% is still going to be more relevant to keeping the company going than other people's 100%.
I wish this was hubris, but no. I would genuninely be happy to not have to do other people's work for them on top of mine.
You wouldn't be the first person to believe himself indispensable who learns otherwise.
> the remaining 10% is still going to be more relevant to keeping the company going than other people's 100%.
Right. Because skills don't atrophy at all.
you are in luck cause you’ll be obsolete and unemployed so you won’t have to worry about anyone’s work on top of yours :)
I’m glad my colleagues and I are all mediocre , because if the alternative is having someone with your arrogance around then no thanks.
I wish I was arrogant. Or alternatively I wish I was surrounded by arrogant coworkers who at least took some pride in the quality and quantity of their work.
Not saying everyone is like this, but plenty enough are.
But hey, at least folks unburdened by the pressure to ship anything have plenty of time to play office politics.
Exactly. How 'bout “economize” chip design by reducing / eliminating human chip designers ... Go figure.
Aren't hardware design issues incredibly costly? I highly doubt they're going to "dark software factory" it or they'll be eaten alive by failed launches, product recalls, lawsuits.
https://en.wikipedia.org/wiki/Pentium_F00F_bug
I worry that even the electronics industry is falling into the fear of being agentic or being left in the dust. AI slop is already weird for programs.. I wouldn't want that in hardware.
Already happening:
https://ashutoshveriprajna.substack.com/p/ai-code-chip-bug-f...
Can't vouch for the source though.
Most of them anyway, and the cutoff bar will continue to rise.
And then the shit won't work, and then they will hire them again lmao
I see this as worse for junior engineers than senior. Right now junior engineers don't have the experience to spot issues, ans if gpt-synopsys gives an answer they don't know to question it. It Will also be better than many junior engineers out of the box.. So junior engineers dont get a chance to learn and progress to senior. Senior engineers (for now) will interact with these agents and review the output, ans can direct them. Again, until it becomes better at that.
Interesting times. A lot has happened in a year..where will we be a year from now?
We just buried an ASIC design that was nearly finished. Reason: There was a deviation that would've needed a mask change, but because of AI chip demand, the manufacturer wanted so much money for it, that we said screw it.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
Nice.
AI didn’t make chip manufacturing more expensive
Manufacturers choosing not to scale with demand or not being able to scale with demand
Is what constrained the supply.
Hopefully will be fixed within a decade , then it’s cool new stuff all the way.
> Manufacturers choosing not to scale with demand or not being able to scale with demand
In a vacuum, that would make sense.
But looking at how the industry works, the number of defunct companies, and how the whole industry got concentrated on the conservative companies, you start to understand that the reason they still exist is mainly because they don't ride fad waves.
It's not like chip manufacturing is a spot instance on AWS that you spin up and down when needed; these are multi-year, multi-billion dollar investments that require long-term demand studies. The AI approach of requesting a whole fab of demand for the next 5 years with a letter from Jason Hwang that says "trust it, bro" does not bring as much confidence as it appears.
Why aren't boring, old process ASICs isolated from this mess?
There’s a lot of other boring chips on a server motherboard beyond the RAM and CPU that share older processes with everyone else making silicon. Stuff like power management ICs needed to bring up power to a chip in the right order, which were an annoyance even before COVID and AI.
The whole supply chain is so focused on RAM/GPUs that it's affecting everything. I've seen random sensors 3x in price because the company making them has shifted their manufacturing focus.
When did chip demand skyrocket?
How long does it take to ramp up capacity?
What kind of deviation? Was it something AI could have helped catch earlier?
Earlier there was no AI to catch it.
Local manufacturing is the next open challenge in hardware. If a pizza can be baked locally, why not chips?
Pizza making smol machine, low precision, child baking big machine, trees expensive, can't have locally
Child baking machine still human job, chip baking is harder
Used to be a bakers oven was one per town, maybe big precise machine becomes cheap smol precise machine
3D printers are a nice analogy, but the complexity level is orders of magnitude higher for chip making, besides the stability of the environment requirements.
From an investment perspective, I think chip fabs TSMC, Intel, and Samsung will benefit from better AI chip design tools.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
Maybe some day, a kid in his garage can just tell an AI to design a custom chip, send it to TSMC, and get the chip in the mail in a few weeks.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
[0]https://fireflies.ai/blog/johny-srouji-and-john-ternus-inter...
[1]https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-...
This might make some sense if, the cost of any change in design vs requirement wouldn't cost $30-50M in mask and tape-out alone. That doesn't count the first wafer 'hot lots' just to get the design's first wafer out in only 3 months, or the bringup and modified test equipment to validate the design, or the corners testing and optimization, or the package tooling, or... Those can easily be additional $10Ms and that's per design, if you do a full mask change. If you can "fix it in metal", you might get that down to just $10M and 1 month?
This isn't software. The time, labor, and equipment costs of the first wafer dwarf the redesign cost, so it makes sense to get it right the first time. What if every build, compile, and link cost you $10M and 1 month? How would that change your work flow?
Most of the "AI" design tools today are focused on verification, validation and layout, which makes a lot of sense. They might help with architecture in the future (or making something high yield AND easy to fix in metal)?
You could run a small design on an MPW shuttle to reduce these costs, but your TTM get's longer, the yields won't be as high, and if you go to mass production you still face the huge mask costs.
Another place this might make some sense is reworking old large die 130nm designs on 8" wafers to be newer 28mm designs on 12", there are a LOT of those. The mask costs are lower, the design is well understood with lots of process margin, and wafer/yield costs could be modeled and favorable. Of course analog scaling is a whole separate kettle of fish.
But then you are assuming the current way is optimal. Why can’t we have a 3d-printer-style contraption for chips?
If people have millions of new chip designs that need making, perhaps that will be motivation to invent a new way of making chips. It might not be better at manufacturing a billion of the same chip, but maybe it’s better at producing a billion different chips. Then every HFT could have their own chip and people could try out all kinds of new designs without committing a fortune.
Can 3D printers print with 1 micrometer (not millimeter) accuracy? 1 micron gets you things like the original 8086. Oh wait, current best desktop printers get like 100 micron (0.1 mm) accuracy. So scale up what we have now 100x in terms of accuracy (imagine how much bigger / more precise the motors, magnets, everything has to be). EASILY 10-50x the cost of a good home 3D printer today - say $50K. And 8086? Your phone is faster than probably 50-100 of them in parallel today) - so $100K (materials aren't cheap) to print a series of chips that were insanely obsolete 20 years ago and 1 $500 fpga could run circles around. Then scale that up at least another 50x to get semi-competitive (20 nm). There's a reason they put fabs in places like Arizona where there are relatively few earthquakes... Even the garbage truck driving past your house could damage your chip.
As far as home printing stuff: the clean room requirements are INSANE: just the HF (hydrofluoric acid) is crazy bad stuff that you could NOT get certified for general consumer use, no way, no how. And even if you did, you'd be crazy to buy something that comes with HF as part of the process.. And that's just ONE bad, bad chemical used by TSMC all the time.
FPGAs are the "faster-than-software / can make a custom chip" compromise - companies like Intel used to (not sure if they still do) use a ton of FGPAs to simulate new chip designs. Precisely because manufacturing state-of-the-art chips is so hard.
Think how long it takes for a 3D printer to finish a single design with 0.1mm resolution. Now scale that down to 10nm. The time to complete goes up by 10^12. A 1 minute design would scale to 2M years.
There's a reason e-beam lithography is only used to make masks, and why it's one of the most expensive parts of the manufacture.
E-beam lithography absolutely is/can be used to manufacture one-off chips.
The problem isn't lithography, though, it's all of the adjacent processes (ion implantation and a dozen other things) that are fab/process-specific and require even more complicated/expensive equipment.
Shuttle runs give you a true-to-process tapeout and are dirt cheap, so only universities and the like bother with direct-write.
> These chips still need to be physically made at TSMC, Intel, or Samsung.
That's for the most advance tech (sub 10nm and such). There is a lot of fab for chips that do not require the latest and greatest. If LLMs make it easier / more accessible to design ASIC, I think those fabs will be the one who will benefit the most.
Yes, there's definitely a demand now for much faster to iterate manufacturing. Even at the cost of quality
TSMC also dominates older fab nodes.
Only tangentially related but many many years ago, I spent a good chunk of a summer internship at synopsys fixing gcc warnings in one of their products. The codebase was huge, with many parts of it more than a decade old at that point. I learned a lot about obscure corners of C. These days a frontier model could do that job in a few days (or maybe just one day if the build and testing process has been sped up - it took several hours on a dedicated cluster back then).
> I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
... > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
EXACTLY, prepare to self deport immediately, push <proceed> to execute
** Disclaimer: I work for Synopsys. **
We also distribute Cadence IP. I know, crazy.
Also the other way around (Cadence shipping Synopsys IP). Big chips wind up with IP blocks from many sources and (at least usually) the right people get paid. And EDA engineers bounce around between Cadence, Synopsys, and Mentor (now Siemens EDA).
„The joint service offering will provide the bundled compute, model, and licenses, while ensuring customer-specific design data is protected.“
I am not sure if Nvidia want to send their chip designs to OpenAI.
its like a fox starting a chicken coop business
OpenAI does, in theory, have ZDR now and private inference soon. But if I'm nvidia I'm not sure how much I would trust it.
Give us more open source EDA tools, not more hyped up EDA vendors.
The goal - obviously - is the exact opposite.
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
A question to those active in chip design industry: Are formal methods and formally proving a design more prevalent and normal in this industry compared to general software development?
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
There are tools for formal verification of design input, and they are being used, but not for everything.
Why there are still errata for silicon
1. Writing a formal specification of your intended behavior is hard and the best verification tool doesn't help when your assertions don't encode the required or intended behavior. So even with 100% formal coverage, you would still get erratas. And some people don't write any formal verification, instead working with a simulation based approach (either hand-written test cases or random stimulus simulation) 2. Computation complexity of formal verification is exponential. At some point you simply can't formally prove the behavior of a design, because it just won't run on your server. 3. There's different levels of formal verification, not all of them are in the spec -> behavior path. For example, you could classify automated checks like logic equivalence between the synthesis netlist and RTL code as a formal verification. But that checks if the optimizer in the synthesis tool was correct, not that you wrote the correct RTL.
It’s called design verification, formal proofs happen mostly at the EDA tool level and largely already automated. Design verification focus on functional correctness of the chip for its intended use case
Compared to software formal methods have greater adoption. But there are a lot of things that fall under the “formal” umbrella.
The most common type that is used would probably be logical equivalence checking. Proving RTL and a netlist are equivalent is useful for catching synthesis bugs.
Or proving two netlists are equivalent after inserting test functions directly into a netlist, or some other netlist edit.
Property checking is what I use the most. You can check these during simulation which I wouldn’t call “formal” but you can also prove them using tools that use SAT solvers and whatnot to prove things mathematically.
As always, the tricky part of verification is writing the correct test or model. With formal we can use SystemVerilog assertions to write properties and sequences, but the difficulty in getting them right goes from trivial -> inscrutable very quickly.
It’s extreme easy to write assertions that pass and never realize your assertion was not doing what you thought and you weren’t proving what you meant to.
I haven’t used some of the more advanced tools so maybe they have ways to make this easier. But because of this I tend to just write assertions that are pretty easy to understand at a glance, and therefore closer to the trivial side of things.
If a peer has to solve a sudoku puzzle in their head to understand your work, then it’s unlikely the peer review will be worth anything. So I do what I can to make my work understandable at a glance (from a competent peer in the industry).
Of course making something simple can be quite challenging and often takes more time than leaving something complex and opaque.
I’ve never been involved in the foundry side of the work, and for ASICs, that is often half of the schedule.
Having written a lot of Tcl glue for PrimeTime and ICC, the hard part was never writing the constraints, it was knowing which timing violation to actually believe.
Apparently SNPS share price gone up a little bit because of this. However, the rise didn't compensate their loss over the years. I keep wondering why EDA companies didn't get the hype like AI labs and Chip design companies.
To maximize hype, a company has to be losing money, but with a story about how it will eventually be making massive money. Stable companies that make some money, are growing steadily but with no hope of growing massively, aren't so exciting, and that's what EDA companies are.
I remember the stock taking a beating after Kimi K3 created all that buzz about the open model designing chips that could run itself (even though the chip in question seemed small in today's standard of massive AI chips). It was only a matter of time before Synopsys released an offering like this. I can almost see the meeting where the C suite demanded working with an external partner over anything in-house they could build.
Why the overall market cap is smaller than both Synopsys and Ansys combined before the merger still beats me tho.
I don't know how much of a difference this makes in practice. Creating the photomasks and proving the resulting silicon is still the predominant bottleneck in chip design.
If you have a flaw in the RTL and need to do a respin it can add 3+ months to the lead time of a new product. Allowing GPT to iterate through this kind of cycle seems economically infeasible unless you have an enormous amount of spare EUV capacity (you don't).
ChatGPT, pretend you are a grizzled hardware engineer and make me a 1nm chip for the iPhone.
Something like JLCPCB but for chips would be revolutionary.
Can't wait for vibe coded SoCs.
Would be really nice honestly. But I don't think it will be coming anytime soon, it's just too expensive to build a chip. The one-time costs for masks are just much more expensive as for PCBs, so wafer shuttle services are still really expensive when pooled PCBs are really cheap. And any machines that would be cheaper for prototyping (direct laser writing or direct e-beam writing) don't scale to mass production.
You can already make (tiny) chips for a somewhat affordable cost with tiny tapeout. But that's still not nearly as cheap as PCB prototypes and with much longer wait times.
Prompt injection in hardware! What could possibly go wrong?
Astra is amazing with open PDKs. ;)
It's hard to believe these probabilistic language model can replace deterministic, precise control of matter needed in hardware design.
You get your non-deterministic process (hired humans or LLMs) to create deterministic scripts (='generators' in EDA terms), which can then be audited, corrected, etc.
DRC/LVS/PEX/SPICE are deterministic, but the tools themselves are not without faults.
Physical design (what this seems to be targeting) already uses non-deterministic algorithms because floorplanning, placement, and routing are all difficult problems to solve with a deterministic algorithm. Introducing probabalistic approaches helps to find the right fit within the constraints.